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400khz 2-wire serial e 2 prom with block lock tm 128k 16k x 8 bit xicor, 1995, 1996 patents pending characteristics subject to change without notice 7027-1.3 5/14/97 t2/c0/d2 sh 1 x24128 functional diagram features ? save critical data with programmable block lock protection ?block lock (0, 1/4, 1/2, or all of e 2 prom array) ?software write protection ? programmable hardware write protect ? in circuit programmable rom mode ? 400khz 2-wire serial interface ? schmitt trigger input noise suppression ?output slope control for ground bounce noise elimination ? longer battery life with lower power ? active read current less than 1ma ?active write current less than 3ma ?standby current less than 1 a ? 1.8v to 3.6v, 2.5v to 5.5v and 4.5v to 5.5v power supply versions ? 32 word page write mode ? minimizes total write time per word ? internally organized 16k x 8 ? bidirectional data transfer protocol ? self-timed write cycle ? typical write cycle time of 5ms ? high reliability ? endurance: 100,000 cycles ?data retention: 100 years ? 14-lead soic ? 16-lead soic ? 8-lead pdip description the x24128 is a cmos serial e 2 prom, internally organized 16k x 8. the device features a serial int er- face and software protocol allowing operation on a simple two wire bus. three device select inputs (s 0 ?s 2 ) allow up to eight devices to share a common two wire bus. a write protect register at the highest address loc a- tion, ffffh, provides three write protection feature s: software write protect, block lock protect, and programmable hardware write protect. the software write protect feature prevents any nonvolatile writ es to the device until the wel bit in the write prote ct register is set. the block lock protection f eature gives the user four array block protect options, se t by programming two bits in the write protect re gister. the programmable hardware write protect featur e allows the user to install the device with wp tied to v cc , write to and block lock the desired porti ons of the memory array in circuit, and then enable the in circuit programmable rom mode by programming the wpen bit high in the write protect register. after this, the block locked portions of the array, inclu ding the write protect register itself, are permanently protected from being erased. serial e 2 prom data and address (sda) scl s2 s1 s0 wp command decode and control logic block lock and write protect control logic device select logic write protect register page decode logic data register y decode logic 4k x 8 4k x 8 8k x 8 write voltage control serial e 2 prom array 16k x 8 7027 fm 01 this x24128 device has been acquired by ic microsystems from xicor, inc.
x24128 2 xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data retention is greater than 100 years. pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output a nd may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, r efer to the pull-up resistor selection graph at the end of this data sheet. device select (s 0 , s 1 , s 2 ) the device select inputs (s 0 , s 1 , s 2 ) are used to set the first three bits of the 8-bit slave address. this allows up to eight devices to share a commo n bus. these inputs can be static or actively drive n. if used statically they must be tied to v ss or v cc as appro- priate. if actively driven, they must be dri ven with cmos levels (driven to v cc or v ss ). write protect (wp) the write protect input controls the hardware write protect feature. when held low, hardware write protection is disabled. when this input is held hig h, and the wpen bit in the write protect register is s et high, the write protect register is protected, preventing changes to the block lock protection and wpen bits. pin names 7027 fm t01 pin configuration symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage nc no connect 16 lead soic 7027 fm 02 v cc wp scl s 0 s 1 nc 1 2 3 4 7 6 5 x24128 v ss sda nc nc nc nc nc s 2 .244? .394? 9 10 11 12 13 14 not to scale nc 8 16 15 nc 8 lead pdip v cc wp scl s 0 s 1 1 2 3 4 6 7 8 x24128 v ss sda s 2 5 .325? .430? 14 lead soic v cc wp scl s 0 s 1 nc 1 2 3 4 7 6 5 x24128 v ss sda nc nc nc nc s 2 .244? .344? 8 9 10 11 12 14 13 nc
x24128 3 device operation the device supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the receivi ng device as the receiver. the device controlling the transfer is a master and the device being controlle d is the slave. the master will always initiate data trans- fers, and provide the clock for both transmit and receive operations. therefore, the device will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condi tion, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and w ill not respond to any command until this condition has bee n met. scl sda data stable data change 7027 fm 03 scl sda start bit stop bit 7027 fm 04 figure 1. data validity figure 2. definition of start and stop
x24128 4 figure 3. acknowle dge response from receiver stop condition all communications must be terminated by a s top condition, which is a low to high transition of sda when scl is high. the stop condition is also used t o place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indica te successful data transfer. the transmitting device , either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock c ycle the receiver will pull the sda line low to ackn owledge that it received the eight bits of data. refer to f igure 3. the device will respond with an acknowledge after recognition of a start condition and its slave addr ess. if both the device and a write operation have been selected, the device will respond with an acknowled ge after the receipt of each subsequent 8-bit word. in the read mode the device will transmit eight bit s of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected an d no stop condition is generated by the master, the devi ce will continue to transmit data. if an acknowledge i s not detected, the device will terminate further data tr ans- missions. the master must then issue a stop conditi on to return the device to the standby power mode and place the device into a known state. scl from master data output from transmitter 1 8 9 data output from receiver start acknowledge 7027 fm 05
x24128 5 figure 4. device addressing 1 s 1 s 0 r/w device select 0 1 0 s 2 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 data byte a2 a1 a0 a5 low order word address a4 a3 word address byte 0 0 a10 a9 a8 0 high order word address a11 x24128 word address byte 1 a13 a12 a7 a6 d0 7027 fm 06 device addressing following a start condition, the master must output the address of the slave it is accessing. the first fou r bits of the slave address byte are the device type ident ifier bits. these must equal ?1010?. the next 3 bits are the device select bits s 0 , s 1 , and s 2 . this allows up to 8 devices to share a single bus. these bits are compared to the s 0 , s 1 , and s 2 device select input pins. the last bit of the slave address byte defines the operation to be performed. when the r/w bit is a on e, then a read operation is selected. when it is zero then a write operation is selected. refer to figu re 4. after loading the slave address byte from the sda bus, th e device compares the device type bits with th e value ?1010? and the device select bits with the status of the device select input pins. if the compare is not suc cessful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. the word address is either supplied by the master or obtained from an internal counter, depending on the operation. the master must supply the two word address bytes as shown in figure 4. the internal organization of the e 2 array is 512 pages by 32 bytes per page. the page address is p artially conta ined in the word address byte 1 and partial ly in bits 7 through 5 of the word address byte 0. the byte address is contained in bits 4 through 0 of the word address byte 0. see figure 4.
x24128 6 figure 6. page write sequence write operations byte write for a write operation, the device requires t he slave address byte, the word address byte 1, and the word address byte 0, which gives the master access to an y one of the words in the array. upon receipt of the word address byte 0, the device responds with an acknowl - edge, and waits for the first eight bits of data. after receiving the 8 bits of the data byte, the device a gain responds with an acknowledge. the master then terminates the transfer by generating a stop condit ion, at which time the device begins the internal write cyc le to the nonvolatile memory. while the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests fro m the master. the sda pin is at high impedance. see figure 5. page write the device is capable of a thirty-two byte page wri te operation. it is initiated in the same manner as th e byte write operation; but instead of terminating th e write operation after the first data word is trans ferred, the master can transmit up to thirty-one more words. th e device will respond with an acknowledge after the receipt of each word, and then the byte add ress is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls o ver? and goes back to the first byte of the current page. this means that the maste r can write 32 words to the page beginning at any byt e. if the master begins writing at byte 16, and loads 32 words, then the first 16 words are written to bytes 16 through 31, and the last 16 words are written to by tes 0 through 15. afterwards, the address counter would point to byte 16. if the master writes more than 32 words, then the previously loaded data is overwritt en by the new data, one byte at a time. the master terminates the data byte loa ding by issuing a stop condition, which causes the d evice to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until comp letion of the internal write cycle. refer to figu re 6 for the address, acknowledge, and data transfer sequence. s t a r t slave address s t o p a c k a c k a c k a c k a c k data (0) signals from the master sda bus signals from the slave (n) word address byte 1 word address byte 0 0 s p data 1 0 1 0 (0 = n = 31) 7027 fm 08 figure 5. byte write sequence signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k a c k word address byte 1 data 1 0 1 0 0 word address byte 0 s p 7027 fm 07
x24128 7 acknowledge polling the maximum write cycle time can be signific antly reduced using acknowledge polling. to initiate acknowledge polling, the maste r issues a start condi- tion followed by the slave address byte for a write or read operation. if the device is still busy with the internal write cycle, then no ack will be returned. if the device has completed the internal write operation, an ack will be returned and the host can then proc eed with the read or write operation. refer to figure 7 . byte load completed by issuing stop. enter ack polling issue start issue slave address byte (read or write) ack returned? high voltage cycle complete. continue sequence? continue normal read or write command sequence proceed issue stop no yes yes issue stop no 7027 fm 09 read operations read operations are initiated in the same manner as write operations with the exception that the r/w bi t of the slave address byte is set to one. there are thr ee basic read operations: current address reads, random reads, and sequential reads. current address read internally, the device contains an address counter that maintains the address of the last word read or writ ten incremented by one. after a read operation f rom the last address in the array, the counter will ?roll o ver? to the first address in the array. after a write operation to the last address in a given page, the counter will ?roll over? to the first address on the same page. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data b yte. the master terminates the read operation when it does n ot respond with an acknowledge during the ninth clock and then issues a stop condition. refer to figure 8 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of th e read operation is not a ?don?t care .? to terminate a read operation, the master must either issue a stop cond i- tion during the ninth cycle or hold sda hig h during the ninth clock cycle and then issue a stop conditi on. from the s t a r t slave address s t o p a c k data signals from the master sda bus signals slave 1 s p 01 0 1 7027 fm 10 figure 7. acknowledge polling sequence figure 8. current address read sequence
x24128 8 random read random read operation allows the master to access a ny memory location in the array. prior to issui ng the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write oper- at ion. the master issues the start condition and the slave address byte with the r/w bit low, receives an acknowledge, then issues the word add ress byte 1, receives another acknowledge, then issues the word address byte 0. after the device acknowl- edges receipt of the word address byte 0, t he master issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge and then eight bi ts of data from the device. the master terminates the read operation by not responding with an acknowl- edge and then issuing a stop condition. refer to figure 9 for the address, acknowledge, and d ata transfer sequence. the device will perform a similar operation called ?set current address? if a stop is issued instead of the second start shown in figure 9. the device will go into standby mode after the stop and all bus activity wi ll be ignored until a start is detected. the effect of th is oper- ation is that the new address is load ed into the address counter, but no data is output by the devic e. the next current address read operation will read from the newly loaded address. sequential read sequential reads can be initiated as either a current address read or random read. the first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device conti nues to output data for each acknowledge received . the master terminates the read operation by not resp onding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from a ddress n followed by the data from address n + 1. the addres s counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. at the end of th e address space the counter ?rolls o ver? to address 0000h and the device continues to output data for each ack nowledge received. refer to figure 10 for the acknowl edge and data transfer sequence. slave address s s t o p a c k a c k a c k a c k data (1) data (2) signals from the master sda bus signals from the slave data (n?1) data (n) 1 (n is any integer greater than 1) p 7027 fm 12 signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k word address byte 1 slave address 0 word address byte 0 s t a r t 1 data a c k s p s 1 0 1 0 7027 fm 11 figure 9. random read sequence figure 10. sequential read sequence
x24128 9 writ e protect register (wpr) writing to the write protect register the write protect register can only be modif ied by performing a ?bytewrite? operation directly to the address ffffh as described below. the data byte must contain zeroes where in dicated in the procedural descriptions below; otherwise the oper- ation will not be performed. only one data byte is allowed for each register write operation. the part will not acknowledge any data bytes after the first byte is entered. the user then has to issue a stop to initi ate the nonvolatile write cycle that writes bl0, bl1, a nd w pen to the nonvolatile bits. a stop must also be is sued after volatile register write operations to put the device into standby. the state of the write protect register can be read by performing a random byte read at ffffh at any time. the part will reset itself after the first byte is read. the master should supply a stop condition to be consist ent with the protocol, but a stop is not required to en d this operation. after the read, the address counter cont ains 0000h. write protect register: wpr (addr = ffff h ) wel: write enable latch (volatile) 0 = write enable latch reset, writes disabled. 1 = write enable latch set, writes enabled. rwel: register write enable lat ch (volatile) 0 = register write enable latch reset, writes to th e w rite protect register disabled. 1 = register write enable latch set, writes to the write protect register enabled. bl0, bl1: block lock protect bits (nonvolatile) the block lock protect bits, bl0 and bl1, determine which blocks of the array are protected. a write to a protected block of memory is ignored, but will rece ive an acknowledge. the master must issue a stop to put the part into standby, just as it would for a valid wri te; but the stop will not initiate an internal nonvolat ile write cycle. see figure 11. wpen: write protect enable bit (nonvolatile) the write protect (wp) pin and the write pr otect enable (wpen) bit in the write protect register control the programmable hardware write protection feature. hardware write protection is enabled when the wp pin is high and the wpen bit is high, and disabled when either the wp pin is low or the wpen bit is low. figure 12 defines the write protect sta tus for each combination of wpen and wp. when the chip is hardware write protected, nonvolatile writes are disabled to the write protect register, inclu ding the block lock protect bits and the wpen bit itself , as well as to the block lock protected sections in the memory array. only the sections of the memory array that are not block lock protected, and the volatile bits wel and rwel, can be written. in circuit programmable rom mode note that when the wpen bit is write protec ted, it cannot be changed back to a low state; so write protection is enabled as long as the wp pin is held high. thus an in circuit programmable rom function can be implemented by hardwiring the wp pin to v cc , writing to and bl ock locking the desired portion of the array to be rom, and then programming the wpen bit high. unused bit positions bits 0, 5 & 6 are not used. all writes to the wpr m ust have zeros in these bit positions. the data byte ou tput during a wpr read will contain zeros in these bits. writing to the wel and rwel bits wel and rwel are volatile latches that power up in the low (disabled) state. while the wel bit is low, writes to any address other than ffffh will be igno red (no acknowledge will be issued after the data by te). the wel bit is set by writing 00000010 to address ffffh. once set, wel remains high until either it i s reset to 0 (by writing 00000000 to ffffh) or until the part powers up again. writes to wel and rwel do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. the rwel bit controls writes to the block lock prot ect bits, bl0 and bl1, and the wpen bit. if rwel is 0 then no writes can be performed on bl0, bl1 , or w pen. rwel is reset when the device powers up or after any nonvolatile write, including writes to th e block lock protect bits, wpen bit, or any bytes i n the memory array. when rwel is set, wel cannot be 7 6 5 4 3 2 1 0 wpen 0 0 bl1 bl0 rwel wel 0
x24128 10 reset, nor can rwel and wel be reset in one write operation. rwel can be reset by writing 00000010 to ffffh; but this is the same operation as in step 3 described below, and will result in programin g bl0, bl1, and wpen. writing to the bl and wpen bits a 3 step sequence is required to change th e nonvola- tile block lock protect or write protect enable bits: 1) set wel=1, write 00000010 to address ffffh (volatile write cycle.) 2) set rwel=1, write 00000110 to address ffffh (volatile write cycle.) 3) set bl1, bl0, and/or wpen bits, write u00xy010 to address ffffh, where u=wpen, x=bl1, and y=bl0. (nonvolatile write cycle.) the three step sequence was created to make it diff i - cult to c hange the contents of the write protect register ac cidentall y. if wel was set to one by a previous register write operation, the user may sta rt at step 2. rwel is reset to zero in step 3 so that use r is required to perform steps 2 and 3 to make another change. rwel must be 0 in step 3. if the rwel bit i n the data byte for step 3 is a one, then no changes are made to the write protect register and the device remains at step 2. the wp pin must be low or the wpen bit must be low before a nonvolatile register write operation is initiated. otherwise, the write op eration will abort and the device will go into standby mode after the master issues the stop condition in step 3. step 3 is a nonvolatile write operation, requiring t wc to complete (acknowledge polling may be used to reduce this time requirement). it should be noted that ste p 3 must end with a stop condition. if a start conditio n is issued during or at the end of step 3 (instead of a stop condition) the device will abort the nonvolatile re gister write and remain at step 2. if the operation is abo rted with a start condition, the master must issue a stop to put the device into standby mode. figure 11. block lock protect bits and protected ad dresses 7027 frm t02 figure 12. wp pin and wpen bit functionality 7027 frm t03 bl1 bl0 protected addresses array location 0 0 none no protect 0 1 3000h - 3fffh upper 1/4 1 0 2000h - 3fffh upper 1/2 1 1 0000h - 3fffh full array wp wpen memory array not lock block protected memory array block lock protected block lock bits wpen bit 0 x unprotected protected unprotected unprotected x 0 unprotected protected unprotected unprotected 1 1 unprotected protected protected protected
x24128 11 absolute maximum ratings* temperature under bias x24128 ....................................... ?65 c to +135 c storage temperature ........................ ?65 c to +150 c voltage on any pin with respect to v ss .................................... ?1v to +7v d.c. output current ............................... ............... 5ma lead temperature (soldering, 10 seconds) .............................. 300 c d.c. operating characteristics 7027 frm t06 capacitance t a = +25 c, f = 1mhz, v cc = 5v 7027 frm t07 notes: (1)must perform a stop command prior to measurement. (2)v il min. and v ih max. are for reference only and are not 100% tested. (3)this parameter is periodically sampled and not 100 % tested. limits symbol parameter min. max. units t est conditions i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 400khz, sda = open, all other inputs = v ss or v cc ? 0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 5 a scl = sda = v cc , all other inputs = v ss or v cc ? 0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 a scl = sda = v cc , all other inputs = v ss or v cc ? 0.3v, v cc = 2.5v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ll (2) input low voltage ?0.5 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma v hys (3) hysteresis of schmitt trigger inputs v cc x 0.05 v symbol parameter max. units test conditions c i/ o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 0 , s 1 , s 2 , scl, wp) 6 pf v in = 0v recommended operating conditions 7027 frm t04 temperature min. max. commercial 0 c +70 c industrial ?40 c +85 c 7027 frm t05 supply voltage limits x24128 4.5v to 5.5v x24128? 2.5 2.5v to 5.5v x24128? 1.8 1.8v to 3.6v *comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional ope ration of the device at these or any other conditi ons above those indicated in the operational sections o f this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
x24128 12 a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & write cycle limits 7027 frm t09 power-up timing (4) 7027 frm t10 notes: (4)t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiate d. these parameters are periodically sampled and not 100% tested. (5)typical values are for t a = 25 c and nominal supply voltage (5v). symbol parameter min. max. units f scl scl clock frequency 0 400 khz t i noise suppression time constant at scl, sda inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus must be free before a new transmission can start 1.2 s t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setup time (for a repeated start condition) 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 100 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t su:sto stop condition setup time 0.6 s t dh data out hold time 50 300 ns t of output fall time 20+0.1c b (5) 250 s symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms a.c. conditions of test 7027 frm t08 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 equivalent a.c. load circuit 5v 1.53k 100pf output 7027 fm 13
x24128 13 symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 7027 fm 17 the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. during the write cycle, the x24128 bus interface ci rcuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 7027 fm 14 write cycle limits 7027 frm t11 symbol parameter min. typ. (5) max. units t wc (6) write cycle time 5 10 ms scl sda 8th bit word n ack t wr stop condition start condition 7027 fm 15 guidelines for calculating typ ical values of bus pull-up resistors 120 100 80 40 60 20 20 40 60 80 100120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k 7027 fm 16 bus timing notes: (5)typical values are for t a = 25 c and nominal supply voltage (5v). (6)t wr is the minimum cycle time to be allowed from the s ystem perspective unless polling techniques are use d. it is the maximum time the device requires to automatically complete the internal write operation. resistance (k )
x24128 14 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14 - lead plastic small outline gullwing package type s note: all dimensions in inches (in parentheses in m illimeters) 0.250" 0.050" t ypical 0.050" t ypical 0.030" t ypical 14 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45
x24128 15 packaging information 16 - lead plastic small outline gull wing package type s 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.386 (9.80) 0.394 (10.01) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 note: all dimensions in inches (in parentheses in m illimeters) 0.250" 0.050" typical 0.030" typical 16 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45 0.050" typical
x24128 16 packaging information note: 1.all dimensions in inches (in parentheses in milli meters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8 - lead plastic dual in - line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62) 7040 fm 18
x24128 17 ordering information part mark convention device x24128 vcc range blank = 5v 10% 2.5 = 2.5v to 5.5v 1.8 = 1.8v to 3.6v temperature range blank = 0 c to +70 c i = ?40 c to +85 c package s14 = 14-lead soic s = 16-lead soic p = 8-lead pdip s = 16-lead soic blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, ?40 c to +85 c ae = 2.5v to 5.5v, 0 c to +70 c af = 2.5v to 5.5v, ?40 c to +85 c ag = 1.8v to 3.6v, 0 c to +70 c ah = 1.8v to 3.6v, ?40 c to +85 c x24128 x x limited warranty devices sold by xicor, inc. are covered by the warr anty and patent indemnification provisions appearin g in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by descri ption regarding the information set forth herein or regarding the freedom of the described devices fro m patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xico r, inc. reserves the right to discontinue productio n and change specifications and prices at any time an d without notice. xicor, inc. assumes no responsibility for the use o f any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the follo wing u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,5 33,846; 4,599,706; 4,617,652; 4,668,932; 4,752, 912; 4,829, 482; 4,874, 967; 4,883, 976. foreig n patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this pro duct should design the system with appropriate error detection and correction, redunda ncy and back-up features to prevent such an occuren ce. xicor's products are not authorized for use in crit ical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical impla nt into the body, or (b) support or sustain life, and whose failure to perform, when properly u sed in accordance with instructions for use provide d in the labeling, can be reasonably expected to result in a significant injury to the u ser. 2.a critical component is any component of a life s upport device or system whose failure to perform ca n be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. p = 8-lead pdip s14 = 14-lead soic g = rohs complaint lead - free package blank = standard package. non lead-free x x x - x

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